1. Technical Field
The present invention relates to the transmission path (or section) of the wireless communication equipments using phase and/or amplitude modulated signals, and more precisely to the signal scaling in such equipments.
2. Description of the Related Art
As it is known by one skilled in the art the transmission path of certain wireless communication equipments, such as GSM or UMTS mobile phones, comprises a signal scaling device to change the gain of the transmit signal. This signal scaling device may be provided in the analog and/or digital part of the transmission path.
A lot of signal scaling devices adapted to gain changes in the digital domain have been proposed. Most of them are multipliers in which the data signals and the chosen gain are binary multiplied via “shift-add-store” procedures. Others are based on look-up tables in which all possible pre-computed values are stored and chosen according to selected addresses. Certain of these devices implement algorithms based on signal processing in the logarithmic domain to reduce the multiplication to a simple binary addition, which is convenient in case of audio or communication signals for which the gain is often given in decibel (dB).
Some signal scaling devices adapted to the gain changes in the analog domain have also been proposed. Such a scaling can either be done in a current mode or in a voltage mode. Some of these devices are based on current scaling via transistor replicas and current mirrors. Others are based on standard operational amplifier architectures comprising resistor or capacitor ratios as gain determining components, as described, for instance, in the document of B. Razavi, “Design of analog CMOS integrated circuits”, McGraw-Hill, New York, 2001.
In both analog and digital domains, the accuracy of the gain change is generally limited to the quantization level used in the basic operations that are involved, i.e., the finite word length in the digital domain or the mismatch/finite component resolution in the analog domain. Therefore these devices may present a low accuracy, which is not satisfactory, or a high complexity with respect to architecture, chip area and/or computation.